The Identify RTL debugger allows you to instrument RTL HDL and then, still at the RT-Level, debug the implemented FPGA on live, running hardware. The Identify FPGA debug software verifies a design in hardware, similar to simulation – only much faster and with in-system stimuli. The Identify RTL debugger allows you to designate sample triggers, navigate the design graphically, and mark signals in the RTL that are to serve as probes. After synthesis, the results are viewed and annotated onto the RTL source code, the HDL Analyst RTL View, or third party, waveform viewer. This ensures RTL-to-implementation equivalence and correct operation of the FPGA design.